1. Technical Field
The present disclosure relates to a substrate for a semiconductor device package, and to a substrate having an external connection pad that narrows, or tapers, from a top surface to a bottom surface and disposed on a pad of a patterned conductive layer.
2. Description of the Related Art
As miniaturization of semiconductor device packages progress, quantity and width/pitch of patterned conductive layers (e.g. pads or traces) in a substrate can be made small. This may present some challenges, such as a misalignment issue, a bridging/short-circuit issue, a thickness issue or other issues.